The present invention is related to systems and methods for semiconductor device testing, and in particular to systems and methods for efficient testing of semiconductor devices that include memory cells.
Various semiconductor devices have been developed that include an EEPROM disposed along with a digital core on a common semiconductor die. FIG. 1 illustrates one such device 100 with a digital core 110 and an EEPROM 120. Digital core 110 is connected to EEPROM 120 via a series of input and output data lines. The input data lines are bi0-bi3, and allow data to be written from digital core 110 to respective EEPROM cells 121 within to EEPROM 120. The output data lines are bo0-bo3, and allow data to be read from respective EEPROM cells 121 within EEPROM 120.
A typical test of device 100 involves writing EEPROM with alternating patterns using data input lines bi0-bi3, and then reading the alternating patterns via data output lines bo0-bo3. The read pattern is compared against the written pattern to determine if there is a short or open associated with input data lines bi0-bi3 or output data lines bo0-bo3, and if respective EEPROM cells 121 are operating properly. An EEPROM write and an EEPROM read may require a substantial amount of time relative to the clock rate of device 100. Thus, completing a full test of device 100 can take a considerable amount of time, and the time required to test the device may be substantially governed by the EEPROM read and/or write time. Further, the amount of time spent testing a single device is multiplied across potentially millions of devices that need to be tested. Thus, the aforementioned approach to device testing is often both costly and inefficient.
Hence, for at least the aforementioned reason, there exists a need in the art for alternative systems and methods for testing various circuitry.